Racetrack memory is counted to be a decent candidate for the next generation of solid state nonvolatile data storage devices. The racetrack memory technology mainly is under development at IBM-Stanford Spintronic Science and Applications Center in a team leading by Stuart Parkin. The key advantages of racetrack memory technology are including its large storage capacity (comparable to disk drives), very fast read/write performance (10,000 times faster than hard disks), lower cost compared to other available memory types, as well as low energy consumption (e.g. compared to MRAM). A racetrack memory is consisted of series of ferromagnetic nanowires with specific number of magnetic domains (data bits) in each wire. By passing a spin-polarized current through these nanowires and due to spin transfer torque effect, magnetic domains can move towards a reading head which is placed closed to the nanowire. Then each magnetic domains’ stray fields are detected by the reading head and interpreted as data bits. Main challenges in front of production of such memories are firstly, finding a method for precise reliable controlling of domains movement forward and backward in nanowires (which can be tuned by changing the current density) and secondly the speed of magnetic domains movement that so far is much slower than what theoretically was expected.